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IEICE Trans

Satoshi ISHII

A Highly Drivable CMOS Design with Very Narrow Sidewall and Novel Channel Profile for 3.3 V High Speed Logic Application
Jiro IDA Satoshi ISHII Youko KAJITA Tomonobu YOKOYAMA Masayoshi INO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/04/25
Vol. E76-C  No. 4  pp. 525-531
Type of Manuscript:  Special Section PAPER (Special Issue on Sub-Half Micron Si Device and Process Technologies)
Category: Device Technology
Keyword: 
CMOS, LDD, hot-carrier-reliability, multiplier, 
 Summary | Full Text:PDF