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IEICE Trans

Satoru NAKAMURA

Self-Reconstruction of 3D Mesh Arrays with 1 1/2-Track Switches by Digital Neural Circuits
Itsuo TAKANAMI Satoru NAKAMURA Tadayoshi HORITA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/09/25
Vol. E82-C  No. 9  pp. 1678-1686
Type of Manuscript:  Special Section PAPER (Special Issue on Integrated Electronics and New System Paradigms)
Category: Configurable Computing and Fault Tolerance
Keyword: 
fault tolerance, three-dimensional mesh array, self-reconstruction, neural algorithm, neural circuit, 
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