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IEICE Trans

Satoru AKIYAMA

A Low-Vt Small-Offset Gated-Preamplifier for Sub-1-V DRAM Mid-Point Sensing
Satoru AKIYAMA Riichiro TAKEMURA Tomonori SEKIGUCHI Akira KOTABE Kiyoo ITOH 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C  No. 4  pp. 600-608
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
low-voltage DRAM, gated preamplifier, mid-point sensing, variations in threshold voltage, 
 Summary | Full Text:PDF
Long-Retention-Time, High-Speed DRAM Array with 12-F2 Twin Cell for Sub 1-V Operation
Riichiro TAKEMURA Kiyoo ITOH Tomonori SEKIGUCHI Satoru AKIYAMA Satoru HANZAWA Kazuhiko KAJIGAYA Takayuki KAWAHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/04/01
Vol. E90-C  No. 4  pp. 758-764
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
Category: Memory
Keyword: 
twin-cell DRAM array, write time, low voltage RAM, retention time, and plate-driven cell, 
 Summary | Full Text:PDF
The Umbrella Cell: A High-Density 2T Cell for SOC Applications
Satoru AKIYAMA Takao WATANABE Nobuhiro OODAIRA Tsuyoshi ISHIKAWA Digh HISAMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/04/01
Vol. E88-C  No. 4  pp. 614-621
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)
Category: Memory
Keyword: 
SOC, on-chip memory, low-voltage, planar capacitor, logic-process, 
 Summary | Full Text:PDF