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IEICE Trans

Ryu OGIWARA

Word-Line Architecture for Highly Reliable 64-Mb DRAM
Daisaburo TAKASHIMA Yukihito OOWAKI Ryu OGIWARA Yohji WATANABE Kenji TSUCHIDA Masako OHTA Hiroaki NAKANO Shigeyoshi WATANABE Kazunori OHUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1992/04/25
Vol. E75-C  No. 4  pp. 501-507
Type of Manuscript:  Special Section PAPER (Joint Special Issue on the 1991 VLSI Circuits Symposium)
Category: 
Keyword: 
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