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IEICE Trans

Ryoto SHIRASAKA

Hardware Efficient and Low Latency Implementations of Look-Ahead ACS Computation for Viterbi Decoders
Kazuhito ITO Ryoto SHIRASAKA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/12/01
Vol. E96-A  No. 12  pp. 2680-2688
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
Viterbi decoding, convolutional code, look-ahead computation, high throughput, 
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