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IEICE Trans

Ryota SHIOYA

Enhancing GPU Performance Through Complexity-Effective Out-of-Order Execution Using Distance-Based ISA
Reoma MATSUO Toru KOIZUMI Hidetsugu IRIE Shuichi SAKAI Ryota SHIOYA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2025/06/01
Vol. E108-D  No. 6  pp. 558-569
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
GPU, microarchitecture, instruction-level parallelism, out-of-order execution, energy efficiency, 
 Summary | Full Text:PDF
A Principal Factor of Performance in Decoupled Front-End
Yuya DEGAWA Toru KOIZUMI Tomoki NAKAMURA Ryota SHIOYA Junichiro KADOMOTO Hidetsugu IRIE Shuichi SAKAI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2023/12/01
Vol. E106-D  No. 12  pp. 1960-1968
Type of Manuscript:  Special Section PAPER (Special Section on Forefront Computing)
Category: 
Keyword: 
instruction fetch, modeling techniques, 
 Summary | Full Text:PDF
Reducing Energy Consumption of Wakeup Logic through Double-Stage Tag Comparison
Yasutaka MATSUDA Ryota SHIOYA Hideki ANDO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2022/02/01
Vol. E105-D  No. 2  pp. 320-332
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
microprocessor, superscalar processor, instruction-level parallelism, issue queue, power consumption, 
 Summary | Full Text:PDF
Skewed Multistaged Multibanked Register File for Area and Energy Efficiency
Junji YAMADA Ushio JIMBO Ryota SHIOYA Masahiro GOSHIMA Shuichi SAKAI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2017/04/01
Vol. E100-D  No. 4  pp. 822-837
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
superscalar processor, register file, multibanking, 
 Summary | Full Text:PDF
Applying Razor Flip-Flops to SRAM Read Circuits
Ushio JIMBO Junji YAMADA Ryota SHIOYA Masahiro GOSHIMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2017/03/01
Vol. E100-C  No. 3  pp. 245-258
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power and High-Speed Chips)
Category: 
Keyword: 
random variation, timing fault detection and recovery, dynamic voltage and frequency scaling (DVFS), SRAM, 
 Summary | Full Text:PDF
Design of a Register Cache System with an Open Source Process Design Kit for 45nm Technology
Junji YAMADA Ushio JIMBO Ryota SHIOYA Masahiro GOSHIMA Shuichi SAKAI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2017/03/01
Vol. E100-C  No. 3  pp. 232-244
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power and High-Speed Chips)
Category: 
Keyword: 
register file, register cache, digital design, freePDK, 
 Summary | Full Text:PDF
FXA: Executing Instructions in Front-End for Energy Efficiency
Ryota SHIOYA Ryo TAKAMI Masahiro GOSHIMA Hideki ANDO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/04/01
Vol. E99-D  No. 4  pp. 1092-1107
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
superscalar processor, hybrid in-order/out-of-order core, energy efficiency, 
 Summary | Full Text:PDF
Improvement of Renamed Trace Cache through the Reduction of Dependent Path Length for High Energy Efficiency
Ryota SHIOYA Hideki ANDO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/03/01
Vol. E99-D  No. 3  pp. 630-640
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
superscalar processor, register renaming, trace cache, energy efficiency, 
 Summary | Full Text:PDF
Performance of Dynamic Instruction Window Resizing for a Given Power Budget under DVFS Control
Hideki ANDO Ryota SHIOYA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/02/01
Vol. E99-D  No. 2  pp. 341-350
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
microprocessor, superscalar processor, memory-level parallelism, instruction-level parallelism, power consumption, 
 Summary | Full Text:PDF
Address Order Violation Detection with Parallel Counting Bloom Filters
Naruki KURATA Ryota SHIOYA Masahiro GOSHIMA Shuichi SAKAI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2015/07/01
Vol. E98-C  No. 7  pp. 580-593
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power and High-Speed Chips)
Category: 
Keyword: 
processor architecture, load-store queue, bloom filter, low-energy technologies, 
 Summary | Full Text:PDF
Register Indirect Jump Target Forwarding
Ryota SHIOYA Naruki KURATA Takashi TOYOSHIMA Masahiro GOSHIMA Shuichi SAKAI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/02/01
Vol. E96-D  No. 2  pp. 278-288
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
processor architecture, register indirect jump, object-oriented programming, 
 Summary | Full Text:PDF
Low-Overhead Architecture for Security Tag
Ryota SHIOYA Daewung KIM Kazuo HORIO Masahiro GOSHIMA Shuichi SAKAI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/01/01
Vol. E94-D  No. 1  pp. 69-78
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
processor architecture, tagged architecture, information security, information flow tracking, 
 Summary | Full Text:PDF