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IEICE Trans

Ryoji SAKURAI

Register-Transfer Level Testability Analysis and Its Application to Design for Testability
Mizuki TAKAHASHI Ryoji SAKURAI Hiroaki NODA Takashi KAMBE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12  pp. 2646-2654
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Test
Keyword: 
testability analysis, register transfer level, design for testability, 
 Summary | Full Text:PDF