Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2018/02/01 Vol. E101-DNo. 2pp. 344-353 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Design Methodology and Platform Keyword: hardware description language, RTL modeling, RTL simulation,
A High Performance FPGA-Based Sorting Accelerator with a Data Compression Mechanism Ryohei KOBAYASHIKenji KISE
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2017/05/01 Vol. E100-DNo. 5pp. 1003-1015 Type of Manuscript: PAPER Category: Computer System Keyword: sorting, hardware accelerator, data compression, open source,