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IEICE Trans

Rin OISHI

FPGA-based Garbling Accelerator with Parallel Pipeline Processing
Rin OISHI Junichiro KADOMOTO Hidetsugu IRIE Shuichi SAKAI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2023/12/01
Vol. E106-D  No. 12  pp. 1988-1996
Type of Manuscript:  Special Section PAPER (Special Section on Forefront Computing)
Category: 
Keyword: 
secure function evaluation, garbled circuit, FPGA, 
 Summary | Full Text:PDF