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IEICE Trans

Renyuan ZHANG

Efficient Hardware Implementation of Robust Binary Neural Networks Using End-to-End Unipolar Representation
Babak GOLBABAEI Yirong KAN Renyuan ZHANG Yasuhiko NAKASHIMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2026/03/01
Vol. E109-A  No. 3  pp. 540-551
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
binary neural networks, stochastic encoding, noise robustness, energy-efficient hardware, resource-constrained environments, 
 Summary | Full Text:PDF
An FPGA Accelerator for Vision Transformer with Quantization and LUT-Based Operations
Cheng XU Yirong KAN Renyuan ZHANG Yasuhiko NAKASHIMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2026/01/01
Vol. E109-D  No. 1  pp. 41-48
Type of Manuscript:  Special Section PAPER (Special Section on Forefront Computing)
Category: 
Keyword: 
vision transformer, FPGA, quantization, acceleration, 
 Summary | Full Text:PDF
GPGPU Implementation of Variational Bayesian Gaussian Mixture Models
Hiroki NISHIMOTO Renyuan ZHANG Yasuhiko NAKASHIMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2022/03/01
Vol. E105-D  No. 3  pp. 611-622
Type of Manuscript:  PAPER
Category: Fundamentals of Information Systems
Keyword: 
GPGPU, Gaussian mixture model, variational Bayes, machine learning, clustering, 
 Summary | Full Text:PDF
A Feasibility Study of Multi-Domain Stochastic Computing Circuit
Tati ERLINA Renyuan ZHANG Yasuhiko NAKASHIMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2021/05/01
Vol. E104-C  No. 5  pp. 153-163
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
stochastic computing, multi-domain, approximate computing, MAC, 
 Summary | Full Text:PDF
Daisy-Chained Systolic Array and Reconfigurable Memory Space for Narrow Memory Bandwidth
Jun IWAMOTO Yuma KIKUTANI Renyuan ZHANG Yasuhiko NAKASHIMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2020/03/01
Vol. E103-D  No. 3  pp. 578-589
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
systolic array, reconfigurable memory space, memory bandwidth, 
 Summary | Full Text:PDF
Programmable Analog Calculation Unit with Two-Stage Architecture: A Solution of Efficient Vector-Computation
Renyuan ZHANG Takashi NAKADA Yasuhiko NAKASHIMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2019/07/01
Vol. E102-A  No. 7  pp. 878-885
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
approximate computing, analog calculation unit, support vector regression, vector-computation, 
 Summary | Full Text:PDF
A ReRAM-Based Row-Column-Oriented Memory Architecture for Convolutional Neural Networks
Yan CHEN Jing ZHANG Yuebing XU Yingjie ZHANG Renyuan ZHANG Yasuhiko NAKASHIMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2019/07/01
Vol. E102-C  No. 7  pp. 580-584
Type of Manuscript:  BRIEF PAPER
Category: 
Keyword: 
data locality, ReRAM, convolutional neural networks, row-column-oriented access, 
 Summary | Full Text:PDF