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IEICE Trans

Rene CUMPLIDO

Design and Implementation of a Non-pipelined MD5 Hardware Architecture Using a New Functional Description
Ignacio ALGREDO-BADILLO Claudia FEREGRINO-URIBE Rene CUMPLIDO Miguel MORALES-SANDOVAL 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/10/01
Vol. E91-D  No. 10  pp. 2519-2523
Type of Manuscript:  LETTER
Category: VLSI Systems
Keyword: 
MD5 algorithm, hardware design, FPGA implementation, hardware architectures, 
 Summary | Full Text:PDF