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IEICE Trans

Piew Yoong CHEE

A 150 MS/s 10-bit CMOS Pipelined Subranging ADC with Time Constant Reduction Technique
Xian Ping FAN Pak Kwong CHAN Piew Yoong CHEE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/05/01
Vol. E92-C  No. 5  pp. 719-727
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
analog-to-digital converter (ADC), subranging ADC, pipeline scheme, CMOS integrated circuit, switched-capacitor circuit, CMOS circuit, 
 Summary | Full Text:PDF