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IEICE Trans

Peter M. LEE

Efficient Application of Hot-Carrier Reliability Simulation to Delay Library Screening for Reliability of Logic Designs
Hisako SATO Mariko OHTSUKA Kazuya MAKABE Yuichi KONDO Kazumasa YANAGISAWA Peter M. LEE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/05/01
Vol. E86-C  No. 5  pp. 842-849
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
hot-carrier, circuit reliability, simulation, delay library, logic design, 
 Summary | Full Text:PDF
Application of Circuit-Level Hot-Carrier Reliability Simulation to Memory Design
Peter M. LEE Tsuyoshi SEO Kiyoshi ISE Atsushi HIRAISHI Osamu NAGASHIMA Shoji YOSHIDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/04/25
Vol. E81-C  No. 4  pp. 595-601
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
hot-carrier degradation, reliability, device lifetime, circuit simulation, SRAM, DRAM, 
 Summary | Full Text:PDF
New Insights in Optimizing CMOS Inverter Circuits with Respect to Hot-Carrier Degradation
Peter M. LEE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/02/25
Vol. E77-C  No. 2  pp. 194-199
Type of Manuscript:  Special Section PAPER (Special Issue on 1993 VLSI Process and Device Modeling Workshop (VPAD 93))
Category: Coupled Device & Circuit Modeling
Keyword: 
integrated electronics, electronic circuits, semiconductor materials and devices, 
 Summary | Full Text:PDF