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IEICE Trans

Peng-Sheng CHEN

A Verification-Aware Design Methodology for Thread Pipelining Parallelization
Guo-An JIAN Cheng-An CHIEN Peng-Sheng CHEN Jiun-In GUO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/10/01
Vol. E95-D  No. 10  pp. 2505-2513
Type of Manuscript:  PAPER
Category: Image Processing and Video Processing
Keyword: 
verification, 3D depth map generation, pipeline, parallel computing, behavior model, 
 Summary | Full Text:PDF