Warning: Undefined array key "abst" in /var/www/02search_html/bin/author.php on line 56

Warning: Undefined array key "abst" in /var/www/02search_html/bin/author.php on line 203

Warning: Undefined array key "abst" in /var/www/02search_html/bin/author.php on line 203

Warning: Undefined array key "abst" in /var/www/02search_html/bin/author.php on line 203

Warning: Undefined array key "abst" in /var/www/02search_html/bin/author.php on line 203

Warning: Undefined array key "abst" in /var/www/02search_html/bin/author.php on line 212

Warning: Undefined array key "abst" in /var/www/02search_html/bin/author.php on line 276

Warning: Undefined array key "abst" in /var/www/02search_html/bin/author.php on line 276

Warning: Undefined array key "abst" in /var/www/02search_html/bin/author.php on line 276

Warning: Undefined array key "abst" in /var/www/02search_html/bin/author.php on line 276

Warning: Undefined array key "abst" in /var/www/02search_html/bin/author.php on line 276

Warning: Undefined array key "abst" in /var/www/02search_html/bin/author.php on line 304

Warning: Undefined array key "abst" in /var/www/02search_html/bin/author.php on line 323
IEICE Trans

Peng-Cheng KAO


An RTL Design-Space Exploration Method for High-Level Applications
Peng-Cheng KAO Chih-Kuang HSIEH Ching-Feng SU Allen C.-H. WU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11  pp. 2648-2654
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High Level Synthesis
Keyword: 
design exploration, high-level synthesis, RTL, design space, AT-curve, 
 Summary | Full Text:PDF