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IEICE Trans

Nobuto UEDA

A Logic Diagnosis Technique for Multiple Output Circuit
Naoaki SUGANUMA Nobuto UEDA Masahiro TOMITA Kotaro HIRANO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/10/25
Vol. E75-A  No. 10  pp. 1263-1271
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
logic diagnosis, logic error location, logic verification, EXM-algorithm, 
 Summary | Full Text:PDF