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IEICE Trans

Nobuhide TAKASHINA

Design for Delay Measurement Aimed at Detecting Small Delay Defects on Global Routing Resources in FPGA
Kazuteru NAMBA Nobuhide TAKASHINA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/08/01
Vol. E96-D  No. 8  pp. 1613-1623
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Test and Verification
Keyword: 
small delay defects, delay measurement, DVMC (delay value measurement circuit), FPGA (field programmable gate array), global routing resource, 
 Summary | Full Text:PDF