A Delay Model of Multiple-Valued Logic Circuits Consisting of Min, Max, and Literal Operations Noboru TAKAGI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/08/01 Vol. E93-DNo. 8pp. 2040-2047 Type of Manuscript: Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing) Category: Logic Design Keyword: multiple-valued logic, multiple-valued logic circuits, hazard detection, delay model,
Decomposition of Surface Data into Fractal Signals Based on Mean Likelihood and Importance Sampling and Its Applications to Feature Extraction Shozo TOKINAGANoboru TAKAGI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/06/01 Vol. E86-ANo. 6pp. 1525-1534 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: multiple-valued logic, static hazard, prime implicants expression,
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/05/25 Vol. E76-DNo. 5pp. 533-539 Type of Manuscript: Special Section PAPER (Special Issue on Multiple-Valued Logic) Category: Logic and Logic Functions Keyword: fuzzy logic, multiple-valued logic, Kleene-Stone algebras, partial order relation,