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IEICE Trans

Naoyuki YOSHIDA

250 Mbyte/s Synchronous DRAM Using a 3-Stage-Pipelined Architecture
Yasuhiro TAKAI Mamoru NAGASE Mamoru KITAMURA Yasuji KOSHIKAWA Naoyuki YOSHIDA Yasuaki KOBAYASHI Takashi OBARA Yukio FUKUZO Hiroshi WATANABE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/05/25
Vol. E77-C  No. 5  pp. 756-761
Type of Manuscript:  Special Section PAPER (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
Category: 
Keyword: 
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