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IEICE Trans

Naoya OKADA

A Field Programmable Sequencer and Memory with Middle Grained Programmability Optimized for MCU Peripherals
Yoshifumi KAWAMURA Naoya OKADA Yoshio MATSUDA Tetsuya MATSUMURA Hiroshi MAKINO Kazutami ARIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/05/01
Vol. E99-A  No. 5  pp. 917-928
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
FPGA, MCU peripherals, field programmable devices, sequencer, SRAM, 
 Summary | Full Text:PDF
Write Control Method for Nonvolatile Flip-Flops Based on State Transition Analysis
Naoya OKADA Yuichi NAKAMURA Shinji KIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/06/01
Vol. E96-A  No. 6  pp. 1264-1272
Type of Manuscript:  Special Section PAPER (Special Section on Circuit, System, and Computer Technologies)
Category: 
Keyword: 
write control method, nonvolatile flip-flop, state transition analysis, clock gating, 
 Summary | Full Text:PDF