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IEICE Trans

Naoya ASADA

Leveraging Different Boolean Function Decompositions to Reduce T-Count in LUT-Based Quantum Circuit Synthesis
David CLARINO Naoya ASADA Atsushi MATSUO Shigeru YAMASHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2025/04/01
Vol. E108-D  No. 4  pp. 320-329
Type of Manuscript:  PAPER
Category: Fundamentals of Information Systems
Keyword: 
relative-phase Toffoli gates (RTOF), circuit optimization, LUT, quantum circuit synthesis, 
 Summary | Full Text:PDF