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IEICE Trans

Nami NAKANO

Study of Reducing Circuit Scale Associated with Bit Depth Expansion Using Predictive Gradation Detection Algorithm
Akihiro NAGASE Nami NAKANO Masako ASAMURA Jun SOMEYA Gosuke OHASHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/05/01
Vol. E97-D  No. 5  pp. 1283-1292
Type of Manuscript:  PAPER
Category: Image Processing and Video Processing
Keyword: 
bit depth expansion, circuit size, IIR filter, gradation pridiction algorithm, 
 Summary | Full Text:PDF