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IEICE Trans

Mudar SAREM

Dynamic Fast Issue (DFI) Mechanism for Dynamic Scheduled Processors
Abderazek BEN ABDALLAH Mudar SAREM Masahiro SOWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12  pp. 2417-2425
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Architecture
Keyword: 
precise interrupt, write-once, parallel, register renaming, out-of-order, 
 Summary | Full Text:PDF