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IEICE Trans

Minoru IIZUKA

An ASIC Design Support Tool Set for Non-pipelined Asynchronous Circuits with Bundled-Data Implementation
Minoru IIZUKA Naohiro HAMADA Hiroshi SAITO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/04/01
Vol. E96-C  No. 4  pp. 482-491
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
asynchronous circuits with bundled-data implementation, latency, ASIC, and design support tool, 
 Summary | Full Text:PDF