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IEICE Trans

Milan VASILKO

A Technique for Modelling Dynamic Reconfiguration with Improved Simulation Accuracy
Milan VASILKO David CABANIS 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11  pp. 2465-2474
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
logic simulation, Dynamically Reconfigurable Logic, run-time reconfiguration, VHDL, FPGAs, 
 Summary | Full Text:PDF