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IEICE Trans

Mathieu MOLONGO

A Fast Three-Layer One-Side Bottleneck Channel Routing with Layout Constraints Using ILP
Kazuya TANIGUCHI Satoshi TAYU Atsushi TAKAHASHI Mathieu MOLONGO Makoto MINAMI Katsuya NISHIOKA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2025/03/01
Vol. E108-A  No. 3  pp. 509-516
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
VLSI layout design, three-layer bottleneck channel routing, integer linear programming, 
 Summary | Full Text:PDF