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IEICE Trans

Masahiro TOMITA

Pattern Generation for Locating Logic Design Errors
Masahiro TOMITA Naoaki SUGANUMA Kotaro HIRANO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/05/25
Vol. E77-A  No. 5  pp. 881-893
Type of Manuscript:  PAPER
Category: Computer Aided Design (CAD)
Keyword: 
binary decision diagram, pattern generation, logic diagnosis, rectification, logic verification, 
 Summary | Full Text:PDF
A Logic Diagnosis Technique for Multiple Output Circuit
Naoaki SUGANUMA Nobuto UEDA Masahiro TOMITA Kotaro HIRANO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/10/25
Vol. E75-A  No. 10  pp. 1263-1271
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
logic diagnosis, logic error location, logic verification, EXM-algorithm, 
 Summary | Full Text:PDF
Lossless Image Compression by Two-Dimensional Linear Prediction with Variable Coefficients
Nobutaka KUROKI Takanori NOMURA Masahiro TOMITA Kotaro HIRANO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/07/25
Vol. E75-A  No. 7  pp. 882-889
Type of Manuscript:  Special Section PAPER (Special Section on Multidimensional Signal Processing)
Category: Image Coding and Compression
Keyword: 
lossless image coding, image compression, 2D linear prediction, 
 Summary | Full Text:PDF