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IEICE Trans

Masahiro KAWAKITA

Regularity-Oriented Analog Placement with Conditional Design Rules
Shigetoshi NAKATAKE Masahiro KAWAKITA Takao ITO Masahiro KOJIMA Michiko KOJIMA Kenji IZUMI Tadayuki HABASAKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/12/01
Vol. E93-A  No. 12  pp. 2389-2398
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword: 
analog placement, regularity-oriented, well-island, sequence-pair, 
 Summary | Full Text:PDF
Image Quality Management for the Super Hi-Vision System at the Kyushu National Museum
Kenichiro MASAOKA Masahiro KAWAKITA Masayuki SUGAWARA Masaru KANAZAWA Kenji OHZEKI Yuji NOJIRI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/11/01
Vol. E89-A  No. 11  pp. 2938-2944
Type of Manuscript:  Special Section PAPER (Special Section on Image Media Quality)
Category: 
Keyword: 
extremely high resolution video system, image processing, MTF, color management, 
 Summary | Full Text:PDF
An Incremental Wiring Algorithm for VLSI Layout Design
Yukiko KUBO Shigetoshi NAKATAKE Yoji KAJITANI Masahiro KAWAKITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/05/01
Vol. E86-A  No. 5  pp. 1203-1206
Type of Manuscript:  Special Section LETTER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
wirability, incremental wiring, channel intersection graph, wire decomposition, 
 Summary | Full Text:PDF
A Global Router for Analog Function Blocks Based on the Branch-and-Bound Algorithm
Tadanao TSUBOTA Masahiro KAWAKITA Takahiro WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/03/25
Vol. E78-A  No. 3  pp. 345-352
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 7th Karuizawa Workshop on Circuits and Systems)
Category: VLSI Design Technology and CAD
Keyword: 
branch-and-bound, layout, global routing, channel-intersection graph, analog, LSI, CAD, 
 Summary | Full Text:PDF
Analog Layout Compaction with a Clean-up Function
Masahiro KAWAKITA Takahiro WATANABE 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1988/12/25
Vol. E71-E  No. 12  pp. 1243-1252
Type of Manuscript:  Special Section PAPER (Special Issue on CAS Karuizawa Workshop)
Category: 
Keyword: 
 Summary | Full Text:PDF