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IEICE Trans

Makoto IMAI

Fast Computational Architectures to Decrease Redundant Calculations -- Eliminating Redundant Digit Calculation and Excluding Useless Data
Makoto IMAI Toshiyuki NOZAWA Masanori FUJIBAYASHI Koji KOTANI Tadahiro OHMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/09/25
Vol. E82-C  No. 9  pp. 1707-1714
Type of Manuscript:  Special Section PAPER (Special Issue on Integrated Electronics and New System Paradigms)
Category: Processors
Keyword: 
MSD-first architecture, digit-serial architecture, numerical characteristic, preprocessing architecture, vector quantization, 
 Summary | Full Text:PDF