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IEICE Trans

Kyohei YAMAGUCHI

MLP-Aware Dynamic Instruction Window Resizing in Superscalar Processors for Adaptively Exploiting Available Parallelism
Yuya KORA Kyohei YAMAGUCHI Hideki ANDO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/12/01
Vol. E97-D  No. 12  pp. 3110-3123
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
microprocessor, superscalar processor, memory-level parallelism, instruction-level parallelism, 
 Summary | Full Text:PDF
Delay Evaluation of Issue Queue in Superscalar Processors with Banking Tag RAM and Correct Critical Path Identification
Kyohei YAMAGUCHI Yuya KORA Hideki ANDO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/09/01
Vol. E95-D  No. 9  pp. 2235-2246
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
microprocessor, superscalar processor, issue queue, delay, complexity, 
 Summary | Full Text:PDF