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IEICE Trans

Kota ASAI

Compaction of Topological Quantum Circuits by Modularization
Kota ASAI Shigeru YAMASHITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2019/04/01
Vol. E102-A  No. 4  pp. 624-632
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
topological quantum computation, qubit layout, circuit optimization, simulated annealing, 
 Summary | Full Text:PDF