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IEICE Trans

Kiyoshi FURUYA

FOREWORD
Kiyoshi FURUYA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/03/01
Vol. E87-D  No. 3  pp. 529-529
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF
Cellular Automata Implementation of TPG Circuits for Built-In Two-Pattern Testing
Kiyoshi FURUYA Naoki NAKAMURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/07/25
Vol. E81-D  No. 7  pp. 675-681
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Diagnosis of VLSI)
Category: Built-in Self-Test
Keyword: 
cellular automata, built-in self-testing, TPG circuit, random pattern generation, 
 Summary | Full Text:PDF
State Diagrams of Elementary Cellular Automata with Arbitrary Boundary Conditions
Poh Yong KOH Kiyoshi FURUYA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/07/25
Vol. E81-D  No. 7  pp. 753-758
Type of Manuscript:  Special Section LETTER (Special Issue on Test and Diagnosis of VLSI)
Category: 
Keyword: 
cellular automata, boundary conditions, transition matrix,  characteristic polynomial, 
 Summary | Full Text:PDF
Stuck-Open Fault Detectabilities of Various TPG Circuits for Use in Two-Pattern Testing
Kiyoshi FURUYA Susumu YAMAZAKI Masayuki SATO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/07/25
Vol. E78-D  No. 7  pp. 889-894
Type of Manuscript:  Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems)
Category: 
Keyword: 
built-in self-test (BIST), two-pattern test, fault coverage, transition coverage, 
 Summary | Full Text:PDF
Design of Autonomous TPG Circuits for Use in Two-Pattern Testing
Kiyoshi FURUYA Seiji SEKI Edward J. McCLUSKEY 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/07/25
Vol. E78-D  No. 7  pp. 882-888
Type of Manuscript:  Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems)
Category: 
Keyword: 
built-in self-test (BIST), two-pattern test, pseudorandom pattern generator, autonomous linear sequential circuit, transition coverage, 
 Summary | Full Text:PDF
Two-Pattern Test Capabilities of Autonomous TGP Circuits
Kiyoshi FURUYA Edward J. McCLUSKEY 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/07/25
Vol. E76-D  No. 7  pp. 800-808
Type of Manuscript:  Special Section PAPER (Special Issue on VLSI Testing and Testable Design)
Category: 
Keyword: 
two-pattern testing, built-in self-test, TPG circuit, linear sequential circuit, transition coverage, 
 Summary | Full Text:PDF
A Method and the Effect of Shuffling Compactor Inputs in VLSI Self-Testing
Kiyoshi FURUYA Edward J. McCLUSKEY 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1992/11/25
Vol. E75-D  No. 6  pp. 842-846
Type of Manuscript:  Special Section PAPER (Special Issue on Pacific Rim International Symposium on Fault Tolerant Systems)
Category: 
Keyword: 
built-in self-testing (BIST), spot error, signature analysis, aliasing, shuffling, 
 Summary | Full Text:PDF
A Probabilistic Approach to Locally Exhaustive Testing
Kiyoshi FURUYA 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1989/05/25
Vol. E72-E  No. 5  pp. 656-660
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
 Summary | Full Text:PDF