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IEICE Trans

Kento YAMAOKA

Statistical Gate-Delay Modeling with Intra-Gate Variability
Kenichi OKADA Kento YAMAOKA Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12  pp. 2914-2922
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Parasitics and Noise
Keyword: 
intra-chip variability, statistical timing analysis, intra-gate variability, manufacturing fluctuation, 
 Summary | Full Text:PDF