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IEICE Trans

Kensuke HINO

Generating Random Benchmark Circuits with Restricted Fan-Ins
Kazuo IWAMA Kensuke HINO Hiroyuki KUROKAWA Sunao SAWADA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/10/25
Vol. E80-D  No. 10  pp. 1009-1016
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Logic Design
Keyword: 
logic optimization, benchmark circuits, random benchmarking, 
 Summary | Full Text:PDF