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IEICE Trans

Kenji KISE

RVCar: An FPGA-Based Simple and Open-Source Mini Motor Car System with a RISC-V Soft Processor
Takuto KANAMORI Takashi ODAN Kazuki HIROHATA Kenji KISE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2022/12/01
Vol. E105-D  No. 12  pp. 1999-2007
Type of Manuscript:  Special Section PAPER (Special Section on Forefront Computing)
Category: 
Keyword: 
FPGA, motor car, Nexys A7, CNN accelerator, RISC-V, soft processor, real time operating system, freeRTOS, 
 Summary | Full Text:PDF
An Efficient Resource Shared RISC-V Multicore Architecture
Md Ashraful ISLAM Kenji KISE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2022/09/01
Vol. E105-D  No. 9  pp. 1506-1515
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
FPGA, soft processor, microarchiteture, multicore, 
 Summary | Full Text:PDF
High-Performance and Hardware-Efficient Odd-Even Based Merge Sorter
Elsayed A. ELSAYED Kenji KISE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2020/12/01
Vol. E103-D  No. 12  pp. 2504-2517
Type of Manuscript:  Special Section PAPER (Special Section on Parallel, Distributed, and Reconfigurable Computing, and Networking)
Category: Computer System
Keyword: 
FPGA, sorting, hardware merge sorter, odd-even sort, merge network, 
 Summary | Full Text:PDF
RVCoreP: An Optimized RISC-V Soft Processor of Five-Stage Pipelining
Hiromu MIYAZAKI Takuto KANAMORI Md Ashraful ISLAM Kenji KISE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2020/12/01
Vol. E103-D  No. 12  pp. 2494-2503
Type of Manuscript:  Special Section PAPER (Special Section on Parallel, Distributed, and Reconfigurable Computing, and Networking)
Category: Computer System
Keyword: 
soft processor, FPGA, RISC-V, RV32I, Verilog HDL, five-stage pipelining, 
 Summary | Full Text:PDF
LEF: An Effective Routing Algorithm for Two-Dimensional Meshes
Thiem Van CHU Kenji KISE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2019/10/01
Vol. E102-D  No. 10  pp. 1925-1941
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
Network-on-Chip, two-dimensional (2D) mesh, routing algorithm, Long Edge First (LEF), 
 Summary | Full Text:PDF
ArchHDL: A Novel Hardware RTL Modeling and High-Speed Simulation Environment
Shimpei SATO Ryohei KOBAYASHI Kenji KISE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2018/02/01
Vol. E101-D  No. 2  pp. 344-353
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Design Methodology and Platform
Keyword: 
hardware description language, RTL modeling, RTL simulation, 
 Summary | Full Text:PDF
A High Performance FPGA-Based Sorting Accelerator with a Data Compression Mechanism
Ryohei KOBAYASHI Kenji KISE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2017/05/01
Vol. E100-D  No. 5  pp. 1003-1015
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
sorting, hardware accelerator, data compression, open source, 
 Summary | Full Text:PDF
Ultrasmall: A Tiny Soft Processor Architecture with Multi-Bit Serial Datapaths for FPGAs
Shinya TAKAMAEDA-YAMAZAKI Hiroshi NAKATSUKA Yuichiro TANAKA Kenji KISE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2015/12/01
Vol. E98-D  No. 12  pp. 2150-2158
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Architecture
Keyword: 
soft processor, processor architecture, FPGA, 
 Summary | Full Text:PDF