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IEICE Trans

Kenichi OSADA

A 2-ns-Access, 285-MHz, Two-Port Cache Macro Using Double Global Bit-Line Pairs
Kenichi OSADA Hisayuki HIGUCHI Koichiro ISHIBASHI Naotaka HASHIMOTO Kenji SHIOZAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2000/01/25
Vol. E83-C  No. 1  pp. 109-114
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
cache, SRAM, low power, two-port, microprocessor, 
 Summary | Full Text:PDF