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IEICE Trans

Keita YASUTOMI

An SOI-Based Lock-in Pixel with a Shallow Buried Channel for Reducing Parasitic Light Sensitivity and Improving Modulation Contrast
Tatsuya KOBAYASHI Keita YASUTOMI Naoki TAKADA Shoji KAWAHITO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2023/10/01
Vol. E106-C  No. 10  pp. 538-545
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Their Application Technologies)
Category: 
Keyword: 
SOI detector, lock-in pixel, parasitic light sensitivity, modulation contrast, 
 Summary | Full Text:PDF
Lock-in Pixel Based Time-of-Flight Range Imagers: An Overview
Keita YASUTOMI Shoji KAWAHITO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2022/07/01
Vol. E105-C  No. 7  pp. 301-315
Type of Manuscript:  INVITED PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
time-of-flight, CMOS image sensors, lock-in pixel, 3-D imaging, charge modulator, 
 Summary | Full Text:PDF
Design of a Digitally Error-Corrected Pipeline ADC Using Incomplete Settling of Pre-Charged Residue Amplifiers
Sung-Wook JUN Lianghua MIAO Keita YASUTOMI Keiichiro KAGAWA Shoji KAWAHITO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/06/01
Vol. E96-C  No. 6  pp. 828-837
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
analog-to-digital conversion, digital error correction, incomplete settling error, pre-charging technique, 
 Summary | Full Text:PDF