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IEICE Trans

Kazuyoshi TAKEMURA

A Practical Method for System-Level Bus Architecture Validation
Kazuyoshi TAKEMURA Masanobu MIZUNO Akira MOTOHARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12  pp. 2439-2445
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Design Methodology
Keyword: 
system-level design, bus architecture validation, bus-cycle-accurate, behavioral model, interface model, 
 Summary | Full Text:PDF