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IEICE Trans

Kazuyoshi NISHIMURA

A 10-Gb/s Burst-Mode Clock-and-Data Recovery IC with Frequency-Adjusting Dual Gated VCOs
Yusuke OHTOMO Masafumi NOGAWA Kazuyoshi NISHIMURA Shunji KIMURA Tomoaki YOSHIDA Tomoaki KAWAMURA Minoru TOGASHI Kiyomi KUMOZAKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/06/01
Vol. E91-C  No. 6  pp. 903-910
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
PON, burst, CDR, IC, CID, 
 Summary | Full Text:PDF
A PVT Tolerant STM-16 Clock-and-Data Recovery LSI Using an On-Chip Loop-Gain Variation Compensation Architecture in 0.20-µm CMOS/SOI
Yusuke OHTOMO Hiroshi KOIZUMI Kazuyoshi NISHIMURA Masafumi NOGAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/04/01
Vol. E91-C  No. 4  pp. 655-661
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
LSI, CDR, CMOS, SOI, jitter, 
 Summary | Full Text:PDF
A Fully Depleted CMOS/SIMOX LSI Scheme Using a LVTTL-Compatible and Over-2, 000-V ESD-Hardness I/O Circuit for Reduction in Active and Static Power Consumption
Yusuke OHTOMO Takeshi MIZUSAWA Kazuyoshi NISHIMURA Hirotoshi SAWADA Masayuki INO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/03/25
Vol. E80-C  No. 3  pp. 455-463
Type of Manuscript:  Special Section PAPER (Special Issue on SOI Devices and Their Process Technologies)
Category: 
Keyword: 
CMOS, SOI, low voltage, LVTTL-compatible, ESD, 
 Summary | Full Text:PDF