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IEICE Trans

Katsuyoshi MIURA

New Approach of Laser-SQUID Microscopy to LSI Failure Analysis
Kiyoshi NIKAWA Shouji INOUE Tatsuoki NAGAISHI Toru MATSUMOTO Katsuyoshi MIURA Koji NAKAMAE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/03/01
Vol. E92-C  No. 3  pp. 327-333
Type of Manuscript:  INVITED PAPER (Special Section on Recent Progress in Superconducting Analog Devices and Their Applications)
Category: 
Keyword: 
SQUID, laser, LSI chip, failure analysis, defect localization, 
 Summary | Full Text:PDF
Hierarchical Fault Tracing for VLSIs with Bi-directional Busses from CAD Layout Data in the CAD-Linked EB Test System
Katsuyoshi MIURA Koji NAKAMAE Hiromu FUJIOKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/03/25
Vol. E80-C  No. 3  pp. 498-502
Type of Manuscript:  LETTER
Category: Integrated Electronics
Keyword: 
bi-directional bus, circuit extraction from CAD layout, electron beam testing, LSI, 
 Summary | Full Text:PDF
Automatic Transistor-Level Performance Fault Tracing by Successive Circuit Extraction from CAD Layout Data for VLSI in the CAD-Linked EB Test System
Katsuyoshi MIURA Koji NAKAMAE hiromu FUJIOKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/11/25
Vol. E78-C  No. 11  pp. 1607-1617
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
performance fault tracing, circuit extraction from CAD layout, electron beam testing, integrated circuits, vacuum and beam technologies, 
 Summary | Full Text:PDF
Matching of DUT Interconnection Pattern with CAD Layout in CAD-Linked Electron Beam Test System
Koji NAKAMAE Ryo NAKAGAKI Katsuyoshi MIURA Hiromu FUJIOKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/04/25
Vol. E77-C  No. 4  pp. 567-573
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Failure Analysis)
Category: 
Keyword: 
vacuum and beam technologies, electron beam testing, pattern matching, CAD layout, 
 Summary | Full Text:PDF
Automatic Tracing of Transistor-Level Performance Faults with CAD-Linked Electron Beam Test System
Katsuyoshi MIURA Koji NAKAMAE Hiromu FUJIOKA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/03/25
Vol. E77-A  No. 3  pp. 539-545
Type of Manuscript:  PAPER
Category: Computer Aided Design (CAD)
Keyword: 
fault analysis, fault tracing, electron beam testing, performance fault, transistor-level circuits, 
 Summary | Full Text:PDF