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IEICE Trans

Kang LI

VLSI Floorplanning with Boundary Constraints Based on Single-Sequence Representation
Kang LI Juebang YU Jian LI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/09/01
Vol. E92-A  No. 9  pp. 2369-2375
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
VLSI physical design, floorplan/placement, boundary constraints, single-sequence, 
 Summary | Full Text:PDF