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IEICE Trans

Jun SAKIYAMA

Counter Tree Diagrams: A Unified Framework for Analyzing Fast Addition Algorithms
Jun SAKIYAMA Naofumi HOMMA Takafumi AOKI Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12  pp. 3009-3019
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: IP Design
Keyword: 
computer arithmetic algorithms, parallel counters, multipliers, datapath, VLSI, circuit synthesis, 
 Summary | Full Text:PDF