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IEICE Trans

Jong-Kyu SONG

A Non-snapback ESD Protection Clamp Circuit Using Isolated Parasitic Capacitance in a 0.35 µm Bipolar-CMOS-DMOS Process
Jae-Young PARK Dae-Woo KIM Young-Sang SON Jong-Kyu SONG Chang-Soo JANG Won-Young JUNG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/05/01
Vol. E94-C  No. 5  pp. 796-801
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
electrostatic discharge (ESD), non-snapback characteristics, gate-coupled effect, isolated parasitic capacitance, Bipolar-CMOS-DMOS process, 
 Summary | Full Text:PDF
On-Chip Charged Device Model ESD Protection Design Method Using Very Fast Transmission Line Pulse System for RF ICs
Jae-Young PARK Jong-Kyu SONG Dae-Woo KIM Chang-Soo JANG Won-Young JUNG Taek-Soo KIM 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/05/01
Vol. E93-C  No. 5  pp. 625-630
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: Analog/RF Devices
Keyword: 
electrostatic discharge (ESD), charged device model (CDM), very-fast transmission line pulse system, low voltage triggered SCR devices, radio pulse integrated circuits (RF ICs), 
 Summary | Full Text:PDF
A Latchup-Free ESD Power Clamp Circuit with Stacked-Bipolar Devices for High-Voltage Integrated Circuits
Jae-Young PARK Jong-Kyu SONG Chang-Soo JANG San-Hong KIM Won-Young JUNG Taek-Soo KIM 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/05/01
Vol. E92-C  No. 5  pp. 671-675
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
ESD (electrostatic discharge) ESD power clamp circuit, latch-up, stacked-bipolar devices, 
 Summary | Full Text:PDF