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IEICE Trans

Jae-Seung HWANG

155-Mb/s Burst-Mode Clock Recovery Circuit Using the Jitter Reduction Technique
Jae-Seung HWANG Chul-Soo PARK Chang-Soo PARK 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2003/04/01
Vol. E86-B  No. 4  pp. 1423-1426
Type of Manuscript:  LETTER
Category: Fiber-Optic Transmission
Keyword: 
burst-mode clock recovery, jitter reduction technique, gated oscillator, 
 Summary | Full Text:PDF