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IEICE Trans

Itsujiro ARITA

Potential of Constructive Timing-Violation
Toshinori SATO Itsujiro ARITA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/02/01
Vol. E85-C  No. 2  pp. 323-330
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors)
Category: High-Performance Technologies
Keyword: 
instruction level parallelism, low power design, fault tolerance, timing constraints, speculative execution, 
 Summary | Full Text:PDF