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IEICE Trans

Ikuo HARADA

A Global Router Optimizing Timing and Area for High-Speed Bipolar LSIs
Ikuo HARADA Yuichiro TAKEI Hitoshi KITAZAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/12/25
Vol. E77-A  No. 12  pp. 2058-2066
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
global routing, timing driven layout, bipolar LSI, delay model, routing graph, critical path, 
 Summary | Full Text:PDF
A Layout System for Mixed A/D Standard Cell LSI's
Ikuo HARADA Hitoshi KITAZAWA Takao KANEKO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1992/03/25
Vol. E75-C  No. 3  pp. 322-332
Type of Manuscript:  Special Section PAPER (Special Issue on Analog LSI and Related Technology)
Category: 
Keyword: 
analog layout, floorplan, placement, global routing, channel routing, crossovers, crosstalk noise, 
 Summary | Full Text:PDF