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IEICE Trans

Hongjie XU

Evaluation Metrics for the Cost of Data Movement in Deep Neural Network Acceleration
Hongjie XU Jun SHIOMI Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2021/11/01
Vol. E104-A  No. 11  pp. 1488-1498
Type of Manuscript:  Special Section PAPER (Special Section on Circuits and Systems)
Category: 
Keyword: 
convolutional neural networks, machine learning, low power circuit design, VLSI, parallel processing, 
 Summary | Full Text:PDF
On-Chip Cache Architecture Exploiting Hybrid Memory Structures for Near-Threshold Computing
Hongjie XU Jun SHIOMI Tohru ISHIHARA Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2019/12/01
Vol. E102-A  No. 12  pp. 1741-1750
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
standard-cell memory, SRAM, near-threshold computing, cache memory, system-on-chip, 
 Summary | Full Text:PDF