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IEICE Trans

Hirotoshi SATO

111-MHz 1-Mbit CMOS Synchronous Burst SRAM Using a Clock Activation Control Method
Hirotoshi SATO Shigeki OHBAYASHI Yasuyuki OKAMOTO Setsu KONDOH Tomohisa WADA Ryuuichi MATSUO Michihiro YAMADA Akihiko YASUOKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/06/25
Vol. E79-C  No. 6  pp. 735-742
Type of Manuscript:  Special Section PAPER (Special Issue on ULSI Memory Technology)
Category: Static RAMs
Keyword: 
memory, synchronous SRAM, high speed SRAM, low power, clock, 
 Summary | Full Text:PDF
A Study of Hierarchical Word Decoding Architecture for ULSI SRAM's
Hirotoshi SATO Shuji MURAKAMI Yasumasa NISHIMURA Toshihiko HIROSE Kenji ANAMI 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1990/11/25
Vol. E73-E  No. 11  pp. 1858-1860
Type of Manuscript:  Special Section LETTER (Special Issue on 1990 Autumn Natl. Conv. IEICE)
Category: Integrated Circuits
Keyword: 
 Summary | Full Text:PDF