IEICE Trans

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IEICE Trans

Hiroaki IWASHITA

Frontier-Based Search for Enumerating All Constrained Subgraphs with Compressed Representation Jun KAWAHARA Takeru INOUE Hiroaki IWASHITA Shin-ichi MINATO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2017/09/01 Vol. E100-A No. 9 pp. 1773-1784 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: zero-suppressed binary decision diagram, froniter-based search, enumeration algorithm, subgraph,
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Efficient Forward Model Checking Algorithm for ω-Regular Properties Hiroaki IWASHITA Tsuneo NAKATA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/11/25 Vol. E82-A No. 11 pp. 2448-2454 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: forward model checking, ω-regular expression, language emptiness check, symbolic model checking, formal verification,
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Integrated Design and Test Assistance for Pipeline Controllers Hiroaki IWASHITA Tsuneo NAKATA Fumiyasu HIROSE
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/07/25 Vol. E76-D No. 7 pp. 747-754 Type of Manuscript: Special Section PAPER (Special Issue on VLSI Testing and Testable Design) Category: Keyword: design verification, test program, VHDL, RISC processor,
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An Extended Digital Fault Simulator for VLSI Circuits Min Sup KANG Hiroaki IWASHITA Isao SHIRAKAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1991/10/25 Vol. E74-A No. 10 pp. 3051-3056 Type of Manuscript: Special Section PAPER (Special Issue on JTC-CSCC '90) Category: VLSI Design Technology Keyword:
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