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IEICE Trans

Hidetsugu IRIE

Enhancing GPU Performance Through Complexity-Effective Out-of-Order Execution Using Distance-Based ISA
Reoma MATSUO Toru KOIZUMI Hidetsugu IRIE Shuichi SAKAI Ryota SHIOYA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2025/06/01
Vol. E108-D  No. 6  pp. 558-569
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
GPU, microarchitecture, instruction-level parallelism, out-of-order execution, energy efficiency, 
 Summary | Full Text:PDF
A Principal Factor of Performance in Decoupled Front-End
Yuya DEGAWA Toru KOIZUMI Tomoki NAKAMURA Ryota SHIOYA Junichiro KADOMOTO Hidetsugu IRIE Shuichi SAKAI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2023/12/01
Vol. E106-D  No. 12  pp. 1960-1968
Type of Manuscript:  Special Section PAPER (Special Section on Forefront Computing)
Category: 
Keyword: 
instruction fetch, modeling techniques, 
 Summary | Full Text:PDF
FPGA-based Garbling Accelerator with Parallel Pipeline Processing
Rin OISHI Junichiro KADOMOTO Hidetsugu IRIE Shuichi SAKAI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2023/12/01
Vol. E106-D  No. 12  pp. 1988-1996
Type of Manuscript:  Special Section PAPER (Special Section on Forefront Computing)
Category: 
Keyword: 
secure function evaluation, garbled circuit, FPGA, 
 Summary | Full Text:PDF
Design and Evaluation of a Configurable Query Processing Hardware for Data Streams
Yasin OGE Masato YOSHIMI Takefumi MIYOSHI Hideyuki KAWASHIMA Hidetsugu IRIE Tsutomu YOSHINAGA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2015/12/01
Vol. E98-D  No. 12  pp. 2207-2217
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
FPGA, query processing, data stream, sliding-window aggregation, configurable hardware architecture, 
 Summary | Full Text:PDF
A Fully Optical Ring Network-on-Chip with Static and Dynamic Wavelength Allocation
Ahmadou Dit Adi CISSE Michihiro KOIBUCHI Masato YOSHIMI Hidetsugu IRIE Tsutomu YOSHINAGA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/12/01
Vol. E96-D  No. 12  pp. 2545-2554
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: 
Keyword: 
Network-on-Chip, high-bandwidth and low power network, optical interconnect, wavelength allocation, 
 Summary | Full Text:PDF
Using Cacheline Reuse Characteristics for Prefetcher Throttling
Hidetsugu IRIE Takefumi MIYOSHI Goki HONJO Kei HIRAKI Tsutomu YOSHINAGA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/12/01
Vol. E95-D  No. 12  pp. 2928-2938
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Computer Architecture
Keyword: 
microarchitecture, cache, prefetch, 
 Summary | Full Text:PDF
Computation-Communication Overlap of Linpack on a GPU-Accelerated PC Cluster
Junichi OHMURA Takefumi MIYOSHI Hidetsugu IRIE Tsutomu YOSHINAGA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/12/01
Vol. E94-D  No. 12  pp. 2319-2327
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: 
Keyword: 
parallel processing, multi-core processor, GPU, computation-communication overlap, 
 Summary | Full Text:PDF
Ultra Dependable Processor
Shuichi SAKAI Masahiro GOSHIMA Hidetsugu IRIE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/09/01
Vol. E91-C  No. 9  pp. 1386-1393
Type of Manuscript:  INVITED PAPER (Special Section on Advanced Processors Based on Novel Concepts in Computation)
Category: 
Keyword: 
microprocessor architecture, dependable computing, attacks, faults, errors, failures, soft errors, timing errors, tamper resistance, information flow, injection attack, dependability manager, 
 Summary | Full Text:PDF